Automatic Design with VHDL & FPGAs (Theory)

Module Information

Module Semester:
5
Module Part:
Theory
Sub-Module Code:
244506
Hours per Week:
2
Module ECTS Credits:
5
Available to ERASMUS Students:
No
Module Staff:


Module Objective

The purpose of the course is the presentation of modern development and design of digital systems, and the implementation and simulation of using VHDL.


Module Study Targets

The learning outcomes of the theoretical part are the following:

  • Identify the modern development and design of digital systems, develop software using VHDL
  • Examine programmable logic devices (PLDs), CPLDs
  • Develop provisions field programmable gateway (FPGA)
  • Compose models for various cutting edge technologies (ASICs)
  • Organize structured methodology to the design of very large systems
  • Explain the Modeling Combinatorial and Sequential Logic
  • Pose Modern and Asynchronous Sequential Circuits
  • Organize modeling and arithmetic units
  • Support the Optimal Implementation and Control Logic Circuits


Module Acquired Abilities

  • Search, analysis and data synthesis
  • Autonomous work
  • Project design


Module Description

Introduction of modern technologies for implementing digital circuits: SSI, Semi-custom, Full-Custom and particularly in programmable logic devices (PLDs), CPLDs and field programmable gate arrays (FPGA). Synthesis of models for various cutting-edge technologies designed for specific applications: application specific integrated circuits (ASICs). Introduction of modern programming languages ​​of description hardware circuits, Data Objects, Commands conforming assignment, project entities in VHDL language, process command, component command. Introduction to learning the VHDL language. Structured methodology to the design of very large systems. Modeling Combinatorial and sequential logic. Modern and Asynchronous Sequential Circuits. Modeling of arithmetic units and Memory Channel. Implementation and control logic optimization. Synthesis with VHDL.


Module Student Evaluation

Students’ evaluation comprises of the :

  • Final exam (60%) and
  • laboratory (40%)


Bibliography

  • Salcic Z. & Smailagic A., "Digital System Design & Prototyping Using FPGA & HDL", Kluwer Academic Publishers, 2000
  • Parhami B., "Computer Arithmetic: Algorithms and Hardware Designs", Oxford Univ. Press, 1999
  • Hayes J., "Computer Architecture and Organization", Mc Graw-Hil, 3rd Edition, 1998
  • Salcic, "VHDL and FPLDs", Kluwer Academic Publishers, 1998
  • Hennessy J.-Patterson D., "Computer Architecture: A Quantitive Approach", Morgan Kaufmann Publishers, 2nd Edition, 1996